With the explosive growth of connected devices, combined with a demand for privacy/confidentiality, low latency and bandwidth constraints, AI models trained in the cloud increasingly need to be run at the edge.

Sipeed’s purpose is a built module designed to run AI at the edge. High performance in a small but powerful footprint, enabling the deployment of high-accuracy AI at the edge, and the competitive price make it possible embed to any IoT devices. Its alot like Google edge TPU, but it acts as  a master controller, not an accelerator like edge TPU, so it is more low cost and low power than AP+edge TPU solution.

Advantage and Usage:

• Provides an end-to-end, hardware + software infrastructure for facilitating the deployment of customers' AI-based solutions.

• Thanks to its performance, small footprint, low power, and low cost, it enables the broad deployment of high-quality.

• It combines custom hardware, open software, and state-of-the-art AI algorithms to provide high-quality, easy to deploy AI solutions.

• Can be used for a number of industrial uses such as predictive maintenance, anomaly detection, machine vision, robotics, voice recognition, and many more.
  * It can be used in manufacturing, on-premise, healthcare, retail, smart spaces, transportation, etc.
  

Sipeed M1 CPU

In hardware, it has  a powerful KPU K210 inside, it offers many excited features:

1st competitive RISC-V chip, also 1st competitive AI chip, newly release in Sep. 2018

28nm process, dual-core RISC-V 64bit IMAFDC, on-chip huge 8MB high-speed SRAM (not for XMR :D), 400MHz frequency (able to 800MHz)

KPU (Neural Network Processor) inside, 64 KPU which is 576bit width, support convolution kernels, any form of activation function. It offers [email protected],400MHz, when overclock to 800MHz, it offers 0.5TOPS. It means you can do object recognition 60fps@VGA

APU (Audio Processor) inside, support 8mics, up to 192KHz sample rate, hardcore FFT unit inside, easy to make a Mic Array (MAIX offer it too)

Flexible FPIOA (Field Programmable IO Array), you can map 255 functions to all 48 GPIOs on the chip

DVP camera and MCU LCD interface, you can connect an DVP camera, run your algorithm, and display on LCD

Many other accelerators and peripherals: AES Accelerator, SHA256 Accelerator, FFT Accelerator (not APU's one), OTP, UART, WDT, IIC, SPI, I2S, TIMER, RTC, PWM, etc.